1. Field of the Invention
The present invention relates to a transmission apparatus that transmits data according to a protocol, and to a method for measuring time in the transmission apparatus.
2. Description of the Related Art
With the spread of gigabit Ethernet® and the like, the ability to execute protocol processing at high speeds is in demand not only for generic PCs but also for embedded devices. It is said that a processor with a processing frequency of approximately 3 GHz is necessary in order to achieve the full-wire speed of gigabit Ethernet®. This greatly exceeds the capabilities of the processors that are generally installed in today's embedded devices. Accordingly, adding a TOE (TCP/IP Offload Engine), which is an auxiliary device designed specifically for protocol processing, to the system in order to implement high-bandwidth network communication is becoming more and more common.
Of great importance in TCP/IP protocol processing is timer processing, which has an integral relationship with protocol processing (see Japanese Patent Laid-Open No. 59-17757). The timer processing is often implemented through a software timer in conventional protocol processing apparatuses. Software timers store timer values in a rewritable storage device, and increment or decrement the timer values in the storage device at set intervals using the processor. The timer is considered to have expired when the timer value reaches a prescribed value, and the processing commences when the timer has expired. With software timers, the number of timers can easily be increased by increasing the capacity of the storage device; however, incrementing or decrementing the counts of all the timers in the storage device at set intervals puts a heavy load on the processor.
A software timer can also be realized by comparing a free running counter that constantly measures time with a timer value in the storage device. With such a software timer, a value obtained by adding a prescribed value to the value of the free running counter at configuration is taken as the timer value. The free running counter and the timer value are compared at a set interval, and the timer is considered to have expired when the two match. Here, as above, while it is not necessary to reset the timer values individually, it is necessary to read out the timer values of all the timers at a set interval and compare them to the free running counter, and thus the increase in the number of timers leads to an increase in the processing load.
Furthermore, in TCP/IP protocol processing, various timers, such as persist timers, delay ACK timers, retransmission timers, keep alive timers, 2MSL (Max Segment Lifetime) timers, and so on, are required at each connection. As a result, when processing several tens to several hundreds of connections, several times that number of timers are required, and thus the processing load for managing the timers will increase almost immeasurably.
Hardware timers (timer controllers) are sometimes used to compensate for the drawbacks of software timers as described above. Such counters are realized by dedicated hardware that has a dedicated register for time counting separate from the memory region and that increments or decrements the count. This dedicated hardware notifies the processor that the timer has expired by outputting an interrupt signal when the timer value reaches a prescribed value. Upon receiving the interrupt signal, the processor temporarily suspends the normal processing, and commences the interrupt process corresponding to the signal after the register, variables, and so on have been saved. Because the processor does not need to increment or decrement the timer value, the load on the processor can be lightened as compared to when using a software timer. It is therefore possible to suppress an increase in traffic to and from the storage device, lighten the processing load on the processor, and so on.
With a timer that uses an interrupt, the interrupt process resulting from the timer is performed in parallel with data transfer any number of times throughout the period in which a TCP connection is established.
Furthermore, in order to implement TCP/IP communication, many timer variables are used based on these timer values. Therefore, it is necessary to secure a sufficient storage region and to use a processor with sufficient timer processing capabilities when performing timer processing in a communications system.
In addition, in a protocol processing apparatus in which the packet transmission/reception processing has been offloaded from the processor, the packet transmission/reception processing is commenced upon a request being made by the processor, and the processor is notified of the completion of the packet transmission/reception processing by an interrupt signal. Having been notified of the completion of the packet transmission/reception processing, the processor starts/stops the timer in accordance with the details of the completed packet transmission/reception processing. With regards to interrupts, U.S. Pat. No. 7,082,486 discloses an interrupt controller capable of performing interrupts by type using an interrupt descriptor table.
With a protocol processing apparatus such as those seen in the aforementioned related art, a timer set including a persist timer, a delay ACK timer, a retransmission timer, a keep alive timer, a 2MSL timer, and so on is necessary per connection when using TCP/IP. When several tens to several hundreds of connections are used, the same number of timer sets as there are connections is used, resulting in a problem that there is an increased load on the processor caused by timer management.
In addition, there are cases, during the transmission/reception of packets, that the delay ACK timer, retransmission timer, and persist timer in this timer set need to be reset frequently, which is a factor in the increase of the load caused by timer management. Furthermore, when a hardware timer is used, the starting/stopping of the timer due to an interrupt also causes processor load. When multiple connections are operating in parallel and timers are frequently started/stopped, the load on the processor increases, reducing the processor resources that can be allocated to other processes.